EDA News Monday May 10, 2004 From: EDACafe ÿÿ Previous Issues _____ http://www.mentor.com/fpga/ _____ About This Issue FPGA Synthesis _____ May 3 - May 7, 2004 By Dr. Jack Horgan Read business product alliance news and analysis of weekly happenings _____ During a phone conversation Jeff Garrison, Director of Product Marketing for FPGA Synthesis Products, divided the FPGA Synthesis market into three segments: Production - FPGA only, no intent for an ASIC implementation Prototyping - intent is to deliver a ASIC implementation Preproduction - use FPGA to satisfy early shipments, switching to ASIC if market demand dictates. The production category includes mainstream/ready-to-use FPGA and PLDs whose design flow is largely push button with low cost tools from FPGA vendors. EDA vendors are targeting the prototype and preproduction segments. According to Gartner Dataquest Synplicty and Mentor Graphics are the industry leading EDA vendors in FPGA synthesis market with each having more than 40% share. Last quarter Synplicity reported total revenue of $13.5 million. FPGA accounted for 75% of bookings in the quarter. The remaining 24% of bookings were for products related to ACICs and Structured/Platform ASICs. Analyzing these numbers suggests that the total existing market for FPGA synthesis (license plus maintenance) is around $100 million on an annual basis. In comparison to ASICs, FGPAs are generally seen as less costly (no NRE), quicker and less risky to develop. Due to their programmability FPGA are more flexible. FPGAs do however have a higher unit cost, consume more power and operate at lower frequencies. These characteristics make them preferable for certain applications, for low to moderate production volumes and for prototyping. They are not well suited for high volume low cost applications such as cell phones. However, times they are a changing. High end FPGAs and FPSoCs are becoming increasing capable, less expensive and faster. Xilinix notes that just a few years ago the largest FPGA was measured in tens of thousands of system gates and operated at 40 MHz. Older FPGAs also were relatively expensive, costing often more than $150 for the most advanced parts at the time. Today, however, FPGAs with advanced features offer millions of gates of logic capacity, operate at 300 MHz, can cost less than $10, and offer a new level of integrated functions such as processors and memory. On the negative side FPGAs are becoming more complex in terms of timing, high utilization, interconnect congestion and signal integrity issues creating a need for more ASIC-like design tools. In a white paper Jeff Wilson of Mentor Graphics said that the FPGA vendors' value-based pricing model makes the performance of a device a major factor in determining final cost. Many design teams use a rule of thumb that assumes the next speed grade increases performance by 12-15% at an additional cost of 20-30%. Turning this around means that improving the performance of a design by 12-15% can mean a silicon cost savings of 20-30%. The exact impact of saving a speed grade will vary, but factors that need to be considered are the device type, number of components in your design, production volume, and your company's purchasing arrangements. The offsetting consideration, of course, is additional design time and effort required to tighten-up design tolerances to reach the new performance targets. The effectiveness of the timing closure process is the deciding factor in what speed grade is ultimately needed for the design. According to an FPGA Project Survey by FPGS and Programmable Logic Journal the most painful and difficult problem for FPGA design teams is getting timing closure on their design. The timing closure process generally involves multiple iterations of RTL modification, constraint specification, synthesis, and place-and-route. On large devices, one pass through this cycle can take more than 24 hours, and some teams are experiencing as many as 50-60 iterations before their design converges. In previous device generations, gate delay accounted for the large portion of the total delay, but with shrinking process technologies and increasing device size and capacity, interconnect delay can exceed 70 percent of the total delay, requiring new approaches to achieving performance targets. The traditional approaches to improve performance include numerous open-ended iterations through synthesis and place-and-route, as well as re-writing the RTL and grouping of cells by floorplanning. While these techniques generally eventually lead to higher performance, both of these increase the number of design iterations unpredictably, and can significantly increase time-to-market. A more promising approach is physical synthesis. Let us see how the vendors are responding to these challenges. Synopsys On March 15th Synopsys announced Design Compiler FPGA (DC FPGA), a new FPGA synthesis product targeted for designers who prototype ASICs using high-end FPGAs. Built upon Synopsys' Design Compiler technology and incorporating new Adaptive Optimization technology, DC FPGA provides designers with an industry standard ASIC-strength solution, the best circuit timing results, and the fastest path to a prototype, through a common ASIC and FPGA flow. At the time of announcement, over 40 customers had purchased DC FPGA and 20 prototype designs had been successfully completed. According to Greg Tanaka, Group Marketing Manager, the number of customers has since doubled. He also reports that Synopsys has added debugging capabilities to the product. Synopsys has had several earlier products in the FPGA Synthesis arena. It introduced FPGA Compiler in 1992, the Windows-based FPGA Express in 1996 and FPGA Compiler II in the late 1990s. None were very successful as measured by market share. Synopsys still sells FPGA Compiler II, but for smaller FPGAs. What has changed? On the marketing front Synopsys found from customer surveys that 42% of their ASIC customers are using FPGA for prototyping. This is consistent with market information from Gary Smith of Gartner/Dataquest on SoC designers. The sweet spot for the DC FPGA product is where there is a combination of high end (greater than .5m ASIC gates) ASIC design flow and where QoR is a critical concern. Synopsys strategy is to leverage its undisputed industry leadership in ASIC synthesis. Synopsys claims that DC FPGA provides three primary benefits to designers. First, customers receive the proven reliability from Synopsys' leading ASIC solution, Design Compiler, whose algorithms have successfully dealt with most challenging ASIC designs (125,000 ASIC tapeouts). The optimization technologies from Design Compiler include finite state machine extraction and optimization, register retiming, advanced resource sharing, register and logic replication, critical path auto ungrouping and more. Next, DC FPGA's Advanced Optimization technology provides 15% better timing than traditional FPGA synthesis solutions. Another benefit is the common ASIC/FPGA flow that gives users the fastest path to prototype because they can design once. Much of code is common with Design Compiler. Synopsys noted that most synthesis offerings are a bag of optimization algorithms typically executed in a fixed order. For any given design some algorithms may have little effect and possibly even a negative effect. The synthesis run time could be reduced by eliminating these algorithms. The quality of results could also be improved by concentrating on those algorithms best suited for the particular design. Synopsys is introducing Adaptive Optimization (AO) technology that automatically activates the best core synthesis algorithms based on multiple parameters, including design size, circuit topology and timing constraints, then dynamically controls and reorders how the algorithms are applied. Synopsys claims that the resulting circuits produced operate, on average, 15 percent faster than those produced by traditional FPGA synthesis products. DC FPGA's compatibility with Design Compiler enables the integration of the ASIC and FPGA design environments. DC FPGA accepts the same RTL code, constraints, scripts, and IP libraries as Design Compiler, and provides the same interface to Formality formal verification. This enables a seamless migration between ASIC and FPGA flows, eliminates manual changes, reduces the possibility of introducing errors in changing between design environments and provides the fastest path to ASIC prototype. Designers prototyping using DC FPGA only need to design once, and benefit from the power of ASIC tools, like Formality, Leda, PrimeTime and the extensive DesignWare libraries for their prototype. Users familiar with DC will come up to speed quickly on Design Compiler FPGA. Gated clocks can be transformed automatically by DC FPGA to FPGA compatible equivalents. This minimizes the clock skew and routing congestion introduced by routing the clock through an FPGA logic element. DC FPGA supports top-down compile. It is also supports true bottom-up synthesis by allowing for flexibility of design style (e.g. incremental synthesis) and the design of different modules by multiple design team members. In addition, through the automated chip synthesis (ACS) capability, Design Compiler FPGA supports distributed synthesis to dramatically reduce runtime. A standalone license of DC FPGA starts at $36,750 for a one-year technology subscription license (TSL). Existing users of Design Compiler may purchase an add-on DC FPGA license for $19,600 for a one-year TSL. Synplicity Synplicity's FPGA products include Synplify Pro for advanced FPGA synthesis, Certify for ASIC RTL prototyping, Identify RTL debugger and Amplify for physical synthesis of FPGAs. Synplify is a high performance logic synthesis engine. Behavior Extraction Synthesis Technology or B.E.S.T is the underlying proprietary technology that the software uses to extract and implement your design structures. During synthesis, B.E.S.T recognizes high-level abstract structures like RAMs , ROMs, FSMs, and arithmetic operators and maintains them at this level instead of converting the design to gates. The technology automatically maps these high-level structures to technology-specific resources using module generators. For example, it maps RAMs to target-specific RAMs, and adders to carry chains. The technology algorithms also optimize hierarchy automatically. The Synplify Pro solution incorporates several advanced optimization techniques, such as retiming. Retiming works by "balancing" the registers across a critical path. The algorithm moves registers across combinatorial logic to improve the timing. Typically, retiming moves flip-flops with no control signals or with minimal control logic. Retiming is timing-based, which means that the software only retimes those critical paths that require it in order to meet timing. One of the strengths of Synplify is the Finite State Machine (FSM) compiler which has the ability to automatically detect state machines in the source code. The state machines are extracted into symbolic graph form, and then special optimizations are performed, including re-encoding of the state representations, which generates a better starting point for the state machines for logic optimization. The FSM Explorer feature determines and uses the best encoding styles for the state machines based on the design constraints and the area/delay requirements. The FSM also perform a reachability analysis to determine all the states that could possibly be reached, and optimize away all states and transition logic that can not be reached. If recovery from an invalid state is important, the "safe" feature can be used to force the state machine to the reset state if an invalid state is reached, with minimal impact on timing and area of the circuit. Multipoint synthesis provides a superior incremental flow and reduces runtime for designs that would take too long for top-down synthesis. The multipoint flow segments designs into smaller synthesis units called compile points. The synthesis software treats each compile point as a block for incremental mapping, which allows the design team to isolate and work on individual compile point modules as independent segments of a larger design without impacting other design modules. A design can have any number of control points and control points can be nested. To use control points effectively, timing constraints (timing budgeting) must be provided for each control point. The Identify tool allows FPGA designers to debug their hardware in a fashion similar to RTL simulators by allowing the control of hardware triggers and viewing of captured data and actual FPGA values directly in the original RTL source code. This provides a significant benefit in the time needed to isolate complex functional problems. Ultra deep submicron processing (UDSP) presents a new and difficult problem for designers. The physical interconnections between logic elements now dominate IC delay. Interconnect can account for as much as 70-90% of overall circuit delay as critical dimensions descend below 0.25çm. Design methods such as conventional logic synthesis fail to adequately account for these effects. Physical synthesis is a superior approach to back-annotation of post-place and route timing and gate-level resynthesis because it actually restructures the logic of a design based on physical characteristics and creates placement. Intelligent reordering of logic with clear mapping to the logic and gate levels represents a vast improvement over the traditional "card shuffling" approach of backannotation. Such restructuring reduces or eliminates iterations between synthesis and place and route, and improves not only productivity but also design performance. Amplify Physical Optimizer features many highly advanced optimization techniques to ensure the best possible performance for a given design. These techniques include critical path restructuring, logic tunneling, feedthrough optimization, constant propagation, logic replication, I/O replication, and wire delay re-timing. The Amplify tool offers the designer the option to implement some or all of these optimization techniques, as specific needs warrant. By performing simultaneous placement and logic optimization, Synplicity claims that the Amplify FPGA product has demonstrated an average of over 21% performance improvement and over 45% improvement in some cases when compared with logic synthesis alone. For prototyping ASICs onto single or multiple FPGA hardware Synplicity offers Certify. The product uses Quick Partitioning Technology (QPT) an automatic RTL partitioning capability. A design can be partitioned with QPT only, manual partitioning then QPT, or QPT followed by manual partitioning changes. Certify software supports probes and multiplexed probes to allow internal debug access. Pricing for the Amplify software starts at $29,000 (U.S.). Pricing for the Synplify software starts at $9,500 and pricing for Synplify Pro software starts at $20,000. Mentor Graphics Mentor's offerings for FPGA synthesis include Precision RTL Synthesis, Precision Physical Synthesis and Precision Physical SA. Precision RTL Synthesis employs a suite of unique algorithms, called Architecture Signature Extraction (ASE) optimization that automatically focuses specific optimizations on areas of the design most likely to hinder overall performance, such as finite state machines, cross-hierarchical paths, and paths with excessive combinational logic. ASE uses an automated, heuristic approach to deliver smaller, faster designs without iterative, manual intervention. Advanced optimization technology breaks down performance-limiting design barriers, such as register, hierarchy, and operator boundaries. A powerful retiming algorithm balances logic across register boundaries; hierarchy optimization minimizes logic between modules; and pipelining moves registers into multipliers. Finite state machines (FSM) are automatically detected and optimized. Complete analysis is performed on each FSM to locate and eliminate all unnecessary states. A variety of encoding styles are then evaluated to determine the best implementation for your design and target technology. On Dec 1st Mentor introduced the Precision Physical Synthesis tool that had been shipping to select customers for twelve months and had been successfully used by multiple companies designing complex FPGA devices. The physical synthesis technologies provide automated physically aware algorithms that use placement and post-place-and-route timing information for retiming, replication and re-synthesis. This can eliminate lengthy design iterations, multiple place-and-route iterations and floorplanning steps. After automation has done as much as possible, the tool offers designers an interactive environment for manual improvements to further tune designs to achieve faster performance or desired speed grades. Precision Physical covers the complete synthesis and design implementation phase of complex FPGA designs. The ability to cross-probe between the timing report, RTL source, RTL schematic and physical views allows users to identify performance bottlenecks, as well as potential functional issues in the design. Based on this information, the design can be debugged and improved quickly. Timing closure problems can be fixed by either modifying the RTL code or optimizing the cell placement. Precision Physical SA (Stand Alone) has the flexibility to start with an EDIF netlist from a variety of synthesis solutions. This netlist is combined with the placement and delay information from place and route and then Precision Physical SA simultaneously optimizes gate and interconnect delay. The output is a fully placed design. Traditionally, FPGA design and PCB design is done separately by distinct design teams using different EDA tools and processes. The existence of multiple design processes creates inter-process connectivity and timing closure problems. FPGA pin counts can exceed 1,500 pins causing time-consuming PCB symbol generation and management tasks. During speed optimization or logic changes, FPGA pin assignment modifications often require time-consuming manual schematic updates and PCB re-routing. Mentor's competitive advantage lies in the integration with its own PCB design tools. Mentor's FPGA BoardLink product automates the critical time-consuming and error-prone tasks faced by the PCB designer. Schematic symbol generation is automatic, utilizing implementation-specific FPGA signal names from the FPGA Advantage tool, while leveraging corporate PCB library information. The user is given the added option of user-directed symbol fracturing allowing high pin count devices to be broken down into multiple symbols. FPGA pin assignments change typically three times or more during a design phase. The FPGA BoardLink product incorporates these pin assignment changes from the FPGA Advantage design environment with automatic updates to the schematic symbol removing the need to re-wire the PCB schematic. The Precision Physical Synthesis product, with integrated RTL synthesis capabilities, starts at $35,000. For existing Precision RTL users, upgrades are available. Afterword Leading FPGA vendors Altera and Xilinx offer their own proprietary synthesis tools as part of their design environment, whereas Actel, Lattice, and QuickLogic all provide OEM versions of Synplicity's Synplify synthesis product. I asked why end users would not use comparatively inexpensive design tools from FPGA vendors like Altera and Xilinx. Simon Block of Mentor said there were three main reasons. First, large system vendors like Motorola or Lucent choose their EDA tools first and their FPGA vendor second. The sizable cost of ownership of EDA tools including support and training for large design staffs demands a single design flow. Second companies prefer multi-vendor, multi-device solutions to avoid being locked in. Finally, the FPGA vendor tools are lacked extended design capabilities and integration with complementary tools. Jeff Garrison added Quality of Result including ability to achieve timing closure as a reason. Letter to the Editor Jack Horgan writes, "If IEEE does not make some accommodation, the donations from Accellera would not become part of Verilog standard for several years." This is incorrect information which has been floating around for many months now. As an active member of IEEE P1364, I can tell you that we are eagerly waiting for the SystemVerilog donation from Accellera. There is full willingness to consider it for the next revision of the IEEE Verilog standard. Shalom Bresticker Response My brief comments were intended to be a statement of fact rather than an attempt to ascribe blame. According to a posting on www.verilog.com the IEEE 1364 Working Group made a call for donations in March of 2003, with a deadline of the end of August 2003. By September 1st of 2003 the group received nine major donations of technology from four companies. The IEEE announced this in a press release on September 4th, 2003. No mention was made of Accellera. As of this writing Accellera has not submitted SystemVerilog to the IEEE. I talked with Michael McNamara, Chairman of 1364 Working Group, and with Dennis Brophy, Chairman of Accellera. While Accellera expressed a goal of having its extensions incorporated into the specification, they have no timetable for submitting their work. Michael said that his group would welcome submissions from Accellera or any other source and would be glad to work with Accellera. He pointed out that the two groups have significant overlap in membership including himself. He was confident that the industry and end users would work to insure that there was one language. As reported in my editorial Accellera Joined IEEE Standards Association (IEEE-SA) in April in order to take part in and shape the direction of technology and its marketplace application. Weekly Industry News Highlights Leading Tech Companies Adopt Cadence Incisive Platform to Reduce Verification Bottlenecks Giga Scale IC Rouses Electronics Industry with InCyte; Industry's First Specification, Optimization Tools Model Nanometer Physical Effects Accellera Announces Formation of Library Characterization & Interoperability Committee, Invites Electronics Industry to Participate UMC and Synopsys Develop Reference Flow for UMC's Advanced Deep Submicron Processes Magma to Develop Low-Power Reference Flow for Nanometer Designs; Industry-Leading IP Providers ARM and Artisan to Collaborate on Flow Development and Validation Magma Announces Blast Power for Power Optimization and Management Mentor Graphics Enhances Designer Productivity for the Ready-to-Use PCB Market with PADS2004 Esterel Technologies Announces SCADE 4.3 Faster, Easier, High-Reliability Embedded Software Development Altera Extends Industry's Lowest-Cost FPGA Configuration Solution Applied Micro Circuits Corporation Completes Acquisition of Intellectual Property and a Portfolio of PowerPC 400 Products Texas Instruments Introduces Cost-Effective, Single-Chip 1394a (FireWire(R)) Link & PHY for Audio/Video Data Connectivity in Consumer Electronics More EDA in the News and More IP & SoC News Upcoming Events... --Contributing Editors can be reached by clicking here . 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